Clarified "Protection" row in "Fields for Rules in Memory Protection" table in the "Memory Protection" section.Added information regarding bus response to memory protection transaction failure in "Memory Protection" section.Added information regarding calculation of ECC error byte address location from erraddr register in "User Notification of ECC Errors" section.Modified text to clarify that there is support for up to 4 Gb external memory device per chip select. In the Memory Protection section - Corrected the "Protection" field definition in the "Fields for Rules in Memory Protection Table". Minor clarifications regarding MPU description and module revision numbersĬorrect SDRAM region address in Arm* Cortex®-A9 MPCore* Address Map.
Added information in ECC Support section regarding ECC errors.Added ACP ID Mapper Address Map and Register Definitions.Added Reset Section to Cortex®-A9 Processor.Added parity error handling information to the "L1 Caches" section and the "Cache Controller Configuration" topic of the "L2 Cache" section.Added a note to the "Control of the AXI User Sideband Signals" subsection in the "ACP ID Mapper" section.Updated HPS Peripheral Master Input IDs table.
#MAC WORD PROCESSOR MANUAL HOW TO#
Clarified how to use fixed mapping mode in the ACP ID Mapper.Added the "Configuration for ACP Use" subsection to the "Accelerator Coherency Port" section.Added the "Shared Requests on ACP" subsection to the "Accelerator Coherency Port" section.Added the "AxUSER and AxCACHE Attributes" subsection to the "Accelerator Coherency Port" section.Added bus transaction scenarios in the "Accelerator Coherency Port" section.Added "L2 Cache Parity" subsection in "L2 Cache" sectionĬlarified EMAC0 and EMAC1 ACP Mapper IDs in the "HPS Peripheral Master Input IDs" table in the "HPS Peripheral Master Input IDs" section.Renamed "ECC Support" L2 subsection to be "Single Event Upset Protection".Added note in the "Implementation Details" subsection of the "ACP ID Mapper" section.Added "Configuring AxCACHE Sideband Signals" and "Configuring AxUser Sideband Signals" subsections to the "AXI Master Configuration for ACP Access" section.Added note to "AXI Master Configuration for ACP Access" section.Introduction to the Hard Processor SystemĪdded Interconnect Master ( L2M0) to the "HPS Peripheral Master Input IDs" table in HPS Peripheral Master Input IDs.Īdded new section Avoiding ACP Dependency LockupĪdded details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section,
#MAC WORD PROCESSOR MANUAL MANUAL#
Arria® V Hard Processor System Technical Reference Manual Revision History Summary Chapter